In many modern digital applications, a clock signal is required to control the timing within the circuitry. Various systems have been developed for generating clock signals. Some of these systems are described in U.S. Pat. Nos. 4,891,825, 5,345,109, 5,371,772, and 5,477,181. Similarly, IBM Technical Disclosure Bulletin Vo. 39, No. 5, pp. 187-188, May 1996 describes a system for an integer divisible frequency divider. IBM Technical Disclosure Bulletin Vol. 30, No. 12, pp. 11-13, May 1988 describes a programmable square wave clock divider. While these references generally describe programmable clock generators, they typically do not provide for variations in duty cycle of the generated clocks. Variations in duty cycle and/or frequency may be useful in several situations which arise in modern digital circuits.
As digital circuits such as processors have increased in speed, the generation of accurate clock signals has generally become more important to assure proper operation of the circuit. For example, as integrated circuits have been designed for low power consumption, clock gating or similar techniques have become a common practice to reduce power. Conventional clock gating utilizes a clock gate signal to deactivate clocks. Typically, the clock to be gated operates at a 50% duty cycle which may result in the clock gate signal needing to arrive before the 50% point of the clock cycle. As clock frequencies have increased, this timing requirement of the gating signal may be difficult to meet. Thus, it may be desirable to change the duty cycle of the clock to allow more time to generate the gate signal.
Another example of a situation where variation of duty cycle and/or frequency may be beneficial is in interfacing to memory. In many designs that interface to memory, such as Dynamic Random Access Memory (DRAM) or on-chip static random access memory (SRAM), the timing requirements of the interface may require use of both edges of the clock. For example, the Column Address Select (CAS) signal for a 70 ns DRAM may have a minimum active time of 10 ns and a minimum inactive time of 15 ns. To maximize performance, it would be desirable to provide a CAS signal with a duty cycle optimized to these requirements. Thus, changing from the conventional 50% duty cycle clock may be beneficial as it may allow timing of the CAS signal to more closely follow the requirements of the memory.
Similarly, pulse shrinkage of clock signals as a result of capacitance on a printed circuit board may be compensated for by altering the duty cycle of the clock. For example, changing the duty cycle of a clock from 50% to 55% may compensate for the capacitance of the printed circuit board so that a 50% duty cycle clock is provided when the pulse shrinks from the capacitance on the printed circuit board.
As the above discussion makes clear, many situations exist where it may be beneficial to adjust the duty cycle or frequency of a clock signal to provide improved timing performance. However, as is also clear from the above discussions, improvements are desirable in existing clock generation systems to provide such dynamic control of timing of the generated clocks.